1. Field of the Invention
This invention relates to particularly a semiconductor memory device whose memory cell unit is constituted by connecting a plurality of memory cells each of which has MOS transistor structure.
2. Description of the Related Art
Recently, an EEPROM with structure designed to attain the high integration density by constituting a memory cell unit having a plurality of memory cells formed as one unit and connecting a data line to the memory cell unit to reduce the number of contacts with the data line is known as an electrically programmable non-volatile semiconductor device (EEPROM) which can be formed with high integration density. For example, an EEPROM having NAND cells each constituted by serially connecting a plurality of memory cells is known. FIG. 1 is a plan view showing one of the NAND cells of this type of EEPROM, and FIGS. 2A and 2B are cross sectional views taken along the lines 2A--2A and 2B--2B of FIG. 1.
A NAND cell having eight memory cells M1 to M8 and two selective transistors S1, S2 is arranged and formed in an area of a p-type silicon substrate 1 (or a wafer having a p-type well formed in an n-type silicon substrate) defined by an element separating insulative film 2. In order to form the memory cells constituting the NAND cell, floating gates 4 (4.sub.1, 4.sub.2, - - - ) of first-layer polysilicon film are formed over the substrate 1 with first gate insulative films 3 disposed therebetween and control gates 6 (6.sub.1, 6.sub.2, - - - ) of second-layer polysilicon film are formed over the floating gates with second gate insulative films 5 disposed therebetween.
The gate insulative films 5a of the selective transistors S1, S2 are formed at the same time as the second gate insulative films 5 and gate electrodes 6a1 and 6a2 thereof are formed at the same time as the control gates 6. The control gate 6 of each memory cell is continuously formed in the row direction to act as a word line. An n-type diffusion layer 7 acting as a source/drain is formed between the memory cells, the adjacent memory cells commonly use the source/drain, and a plurality of memory cells are serially connected to constitute the NAND cell.
The write and erase operations of the NAND-type cell EEPROM are effected by transferring charges by a tunneling current flowing between the substrate 1 and the floating gate 4. The NAND-type cell EEPROM has an advantage over the conventional NOR type EEPROM that the number of contacts can be significantly reduced and the high integration density can be attained.
However, if attempts are made to further increase the integration density of the EEPROM, the following problem which must be solved occurs.
The area of a portion other than the memory cells, particularly the area occupied by the selective transistors S1, S2 must be reduced. In the case of NAND cell, the selective transistors S1, S2 are necessary and indispensable to attain the selectivity with the adjacent NAND cell. Further, owing to the high resistance of the diffusion layer of the source line, a sufficiently large cell current cannot be obtained and high-speed access cannot be attained. Since the punch-through breakdown voltage of the selective gate is lowered because of miniaturization of the elements, the gate length of the selective gate cannot be reduced, thereby the area of the selective gate section cannot be reduced.
As described above, in the conventional non-volatile semiconductor memory device, the area occupied by the selective transistor portion cannot be reduced, making it more difficult to enhance the integration density. Further, the high-speed access cannot be attained and the problem that the punch-through breakdown voltage is lowered occurs.